Thermal process for implementing the planarization inherent to s

Details Thermal process for implementing the planarization inherent to s Thermal process for implementing the planarization inherent to s

1991-04-18

1992-06-09

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 42, 437979, 437985, H01L 21311

Patent

active

051206706

ABSTRACT:
The present invention provides a method of fabricating a virtual ground EPROM cell in a silicon substrate of P-type conductivity. In accordance with the method, a gate oxide layer is formed on the silicon substrate. This is followed by the formation of a first layer of polysilicon (poly 1). Next, a composite structure comprising oxide-nitride-oxide (ONO) is formed on the first polysilicon layer. Next, a photoresist mask is used to define parallel lines of ONO/poly 1. After etching the ONO/poly 1 to define the parallel lines, an arsenic implant is performed while keeping the photoresist mask in place to define N+ bit lines between the lines of ONO/poly 1. After the photoresist is stripped from the parallel lines of ONO/poly 1, an oxidation step is performed to complete the oxidation of the ONO and to simultaneously grow a differential oxide between the lines of ONO/poly 1. In the subsequent etching of the ONO/poly 1 lines in a stacked etch procedure, the differential oxide overlying the N+ bit lines protects the underlying substrate, thus avoiding interruption ("digging") of N+ bit lines in the EPROM array.

REFERENCES:
patent: 4795719 (1989-01-01), Eitan
patent: 4833514 (1989-05-01), Esquivel et al.
patent: 4849369 (1989-07-01), Jeuch et al.
patent: 4861730 (1989-08-01), Hsia et al.
patent: 4892840 (1990-01-01), Esquivel et al.
patent: 5028553 (1991-07-01), Esquivel et al.

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