Method of manufacturing semiconductor device having multilayer i

Details Method of manufacturing semiconductor device having multilayer i Method of manufacturing semiconductor device having multilayer i

1995-12-20

1997-12-23

Graybill, David

Fishing, trapping, and vermin destroying

437228, 437231, 4272553, 4272557, H01L 2144

Patent

active

057007209

ABSTRACT:
According to the method of manufacturing a semiconductor device having a multilayer interconnection structure, lower wires are formed on a semiconductor substrate. Then, a first reflow SiO.sub.2 film having a reflow form is formed on the semiconductor substrate and the lower wires by reacting SiH.sub.4 gas with H.sub.2 O.sub.2 in a vacuum at 650 Pa or less within a range from -10 to 10.degree.C. After the first reflow SiO.sub.2 film is formed, heat treatment is performed at a predetermined high temperature on the semiconductor substrate on which the first reflow SiO.sub.2 film, and a second reflow SiO.sub.2 film having a reflow form is formed on the semiconductor substrate and the lower wires by reacting SiH.sub.4 gas with H.sub.2 O.sub.2 in a vacuum at 650 Pa or less within a range from -10 to 10.degree.C. The heat treatment step performed after the first reflow SiO.sub.2 film forming step and the second reflow SiO.sub.2 film forming step subsequent thereto are respectively performed at least once. After the abovementioned steps are finished, upper wires are formed on the second reflow SiO.sub.2 film.

REFERENCES:
patent: 5314724 (1994-05-01), Tsukune et al.
patent: 5387546 (1995-02-01), Maeda et al.
Dobson et al, Semicond. Int. pp. 85-88 (1994).
Matsuura et al IEDM vol. 94 pp. 117-120 (IEEE 1994).
Dobson et al., "Advanced SiO.sub.2 Planarization Using Silane and H.sub.2 O.sub.2 ", Semiconductor International, pp. 85-88, (1994).
Matsuura et al., "Novel Self-planarizing CVD Oxide for Interlayer Dielectric Applications", IEEE, pp. 5.7.1-5.7.4, (1994).

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