Process for fabricating storage capacitor for DRAM memory cell

Details Process for fabricating storage capacitor for DRAM memory cell Process for fabricating storage capacitor for DRAM memory cell

1996-06-18

1997-12-23

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 60, 437919, 437 47, H01L 218242

Patent

active

057007080

ABSTRACT:
A process for fabricating a storage capacitor for memory cell units of a DRAM memory device to achieve an increased capacitance value. The process includes first forming a transistor including a gate, a source region, and a drain region on the silicon substrate of the device. The gate includes a first polysilicon layer covered by an insulating layer. A silicon nitride layer is formed covering the transistor and a silicon oxide layer is formed on the silicon nitride layer. A contact opening is formed in the silicon oxide layer and the silicon nitride layer which exposes the surface of the transistor drain/source region. The silicon oxide layer has an edge portion extending toward the cavity of the contact opening more than the edge of the silicon nitride layer below it extends. A second polysilicon layer is then formed in the contact opening, covering the exposed drain region, the gate, and the edge portion of the silicon oxide layer and the silicon nitride layer. The second polysilicon layer thus provides the first electrode of the storage capacitor. A dielectric layer is formed on the second polysilicon layer to provide the dielectric of the storage capacitor and a third polysilicon layer is formed on the dielectric layer to provide the second electrode of the storage capacitor.

REFERENCES:
patent: 5145801 (1992-09-01), Chhabra
patent: 5290726 (1994-03-01), Kim
patent: 5330928 (1994-07-01), Tseng
patent: 5384276 (1995-01-01), Ogawa et al.
patent: 5422295 (1995-06-01), Choi et al.
patent: 5436188 (1995-07-01), Chen

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