Method for screening non-volatile memory and programmable logic

Details Method for screening non-volatile memory and programmable logic Method for screening non-volatile memory and programmable logic

1995-07-10

1997-12-23

Niebling, John

Fishing, trapping, and vermin destroying

437 52, 437 43, 324523, 324769, H01L 218217, H01L 2166

Patent

active

057006989

ABSTRACT:
An improved method for screening a non-volatile memory device or programmable logic device including the steps of initially programming and then erasing a device for a predetermined number of cycles thereby providing a stressed device. Next, the stressed device is erased, providing an erased device. A first voltage value is measured across the floating gate of each cell of the erased device which is then stored for a predetermined period of time at a first predetermined temperature, providing a stored device. Next, the stored device is baked at a second predetermined temperature resulting in a baked device. Then, a second voltage value is measured across the floating gate of each cell of the baked device. Each of the first and the second voltage values are subtracted to provide a plurality of measured voltage drop values each of which are compared to an acceptable predetermined voltage drop value. The baked device is identified as defective and is discarded if any of the measured voltage drop values are greater than the acceptable predetermined voltage drop value. The first predetermined temperature is room temperature (i.e., 0.degree.-50.degree. C.), and the second predetermined temperature is greater than or equal to 250.degree. C.

REFERENCES:
patent: 4607219 (1986-08-01), Isosaka
patent: 4918377 (1990-04-01), Buehler et al.
patent: 5032786 (1991-07-01), Kimura
patent: 5298433 (1994-03-01), Furuyama
patent: 5381103 (1995-01-01), Edmond et al.
patent: 5394101 (1995-02-01), Mitros

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