Method for packaging an integrated circuit using a reconstructed

Details Method for packaging an integrated circuit using a reconstructed Method for packaging an integrated circuit using a reconstructed

1995-06-06

1997-12-23

Graybill, David

Fishing, trapping, and vermin destroying

437210, 437217, 437220, 437923, 437974, H01L 2158, H01L 2128, H01L 2148, H01L 2156

Patent

active

057006970

ABSTRACT:
A reconstructed package for an integrated circuit (IC) chip and a method of re-configuring any prefabricated IC package (with or without a silicon chip and wires inside) so that an IC chip can be installed and interconnected for normal use. A pre-molded plastic or other package is abraded to expose the wire bond pads and to form a mounting surface to which a new chip may be mounted. The encapsulating material is removed without damaging the plating material on the lead frame. The new chip is then mounted onto the mounting surface and new wire bonds are connected between the new chip and the lead frame. Encapsulating material, such as epoxy, is then placed over the chip and wire bonds and cured. The invention provides an alternative process whereby the die can be encapsulated in minutes per unit.

REFERENCES:
patent: H1379 (1994-12-01), Meuer
patent: 3482419 (1969-12-01), Rogers et al.
patent: 3627901 (1971-12-01), Happ
patent: 3762039 (1973-10-01), Douglass et al.
patent: 3969813 (1976-07-01), Minetti et al.
patent: 4089704 (1978-05-01), Heiss, Jr. et al.
patent: 4359360 (1982-11-01), Harris et al.
patent: 4384917 (1983-05-01), Wensink
patent: 4474621 (1984-10-01), Saccocio et al.
patent: 4567006 (1986-01-01), Covington et al.
patent: 4691225 (1987-09-01), Murakami et al.
patent: 4768286 (1988-09-01), Ketcham
patent: 4914813 (1990-04-01), Layher et al.
patent: 4980019 (1990-12-01), Baerg et al.
patent: 5041396 (1991-08-01), Valero
patent: 5138430 (1992-08-01), Gow et al.
patent: 5149662 (1992-09-01), Eichelberger
patent: 5155068 (1992-10-01), Tada
patent: 5180093 (1993-01-01), Stansbury et al.
patent: 5252179 (1993-10-01), Ellerson et al.
patent: 5398926 (1995-03-01), Dlugokecki
patent: 5406117 (1995-04-01), Dlugokecki et al.
patent: 5424254 (1995-06-01), Damiot
"Repair Technology for Modules", W. K. Spielmann et al., IBM Technical Disclosure Bulletin vol. 10, No. 11, p. 1810, Apr. 1968.
Novus Technologies, Inc. Promotional Literature; (no date available) 1423 San Rafael Ave. NE, P.O. Box 53416, Aluquerque, NM 87153.
ICOM Corporation Promotional Literature; (no date available) 734 Silver Spur Rd., Ste. 201, Rolling Hills Estates, CA 90274.

Affiliated with

Also associated with

Rating

Method for packaging an integrated circuit using a reconstructed does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for packaging an integrated circuit using a reconstructed, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for packaging an integrated circuit using a reconstructed will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1802111