Apparatus for selectively exposing a semiconductor topography to

Chemistry: electrical and wave energy – Apparatus – Electrolytic

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204224M, 204225, C25F 700

Patent

active

059482192

ABSTRACT:
A lithographic apparatus and method are presented which use an electric field to form features from a desired material upon an upper topography of a semiconductor substrate. A layer of an electric field resist material is formed over a layer of the desired material upon the upper topography of the semiconductor substrate. The electric field resist layer is then patterned by exposure to an electric field via the apparatus. The apparatus includes a plate and a voltage source. In one embodiment, the plate is electrically conductive and a lower surface of the plate has one or more raised portions with recessed portions existing between adjacent raised portions. The lower surface of the conductive plate is positioned above and in close proximity to the exposed surface of the electric field resist layer. The voltage source applies an electrical voltage between the electrically conductive plate and the semiconductor substrate, creating the electric field. The strength of the electric field between raised portions of the conductive plate and the semiconductor substrate is great enough to: (i) cause polymerized molecules within the electric field resist layer to break apart (positive resist layer), or (ii) cause unpolymerized molecules within the electric field resist layer to polymerize (negative resist layer). Following the exposing step, the unpolymerized electric field resist material is removed, followed by a portion of the layer of the desired material not covered by the remaining polymerized portion of the electric field material and the remaining polymerized portion of the electric field material.

REFERENCES:
patent: 4110190 (1978-08-01), Visser
patent: 5160590 (1992-11-01), Totsuka et al.
patent: 5217586 (1993-06-01), Datta et al.

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