Fine dimension stacked vias for a multiple layer circuit board s

Details Fine dimension stacked vias for a multiple layer circuit board s Fine dimension stacked vias for a multiple layer circuit board s

1995-09-25

1997-12-23

Vo, Peter

Metal working

Method of mechanical manufacture

Electrical device making

29830, 29884, 174264, 361795, 427 97, H05K 310

Patent

active

056996136

ABSTRACT:
A method of manufacturing a multiple layer circuit board with stacked vias of fine dimension and pitch. A base laminate with conductive pattern is coated with a dielectric which is photolithographically processed to create holes exposing selected regions of the underlying conductive pattern. The holes through the dielectric are plated to form via connections between the surface and the conductive pattern on the base laminate. The recess created by the via is filled with a conductive and plateable polymer which upon curing forms a conductive plug. A second dielectric layer is deposited on the board structure and in succession photolithographically processed to expose the underlying plated via and plug. The hole in the second dielectric is plated and filled with conductive polymer so as to create a second via vertically aligned with and electrically connected to the underlying first via. The ability to form fine pitch stacked vias is particularly important for printed circuit board structures such as carriers of flip chip die, in that the fine pitch of the solder ball array of the flip chip needs to be expanded and/or disbursed through multiple board layers with minimum area and electrical degradation.

REFERENCES:
patent: 4673773 (1987-06-01), Nakano et al.
patent: 4908940 (1990-03-01), Amano et al.
patent: 5006182 (1991-04-01), Gantzhorn, Jr. et al.
patent: 5098771 (1992-03-01), Friend
patent: 5123849 (1992-06-01), Deak et al.
patent: 5129142 (1992-07-01), Bindra et al.
patent: 5200112 (1993-04-01), Angelopooulos et al.
patent: 5232548 (1993-08-01), Ehrenberg et al.
patent: 5263243 (1993-11-01), Taneda et al.
patent: 5300402 (1994-04-01), Card, Jr. et al.
patent: 5327013 (1994-07-01), Moore et al.
patent: 5346558 (1994-09-01), Mathias
patent: 5376403 (1994-12-01), Capote et al.
patent: 5378402 (1995-01-01), Cross et al.
patent: 5487218 (1996-01-01), Bhatt et al.
patent: 5509203 (1996-04-01), Yamashita
IBM Technical Disclosure Bulletin, vol. 36, No. 05, May 1993, "Method of Adding Devices to a Finished Circuit Card or Panel", p. 207.
IBM Technical Disclosure Bulletin, vol. 4, No. 2, Jul. 1961, "Solderable Contact Adhesive", pp. 15-16.
VLSI Technology, S. M. Sze, 1983, pp. 554-555.

Affiliated with

Also associated with

Rating

Fine dimension stacked vias for a multiple layer circuit board s does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fine dimension stacked vias for a multiple layer circuit board s, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fine dimension stacked vias for a multiple layer circuit board s will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1794051