Interleaved memory wherein plural memory means comprising plural

Details Interleaved memory wherein plural memory means comprising plural Interleaved memory wherein plural memory means comprising plural

1993-05-06

1996-07-16

Swann, Tod R.

Boots, shoes, and leggings

3642464, 364251, 3642511, 364DIG1, 3649606, 36496433, 3649663, 364DIG2, 39542109, 395454, 395477, G06F 1200

Patent

active

055375774

ABSTRACT:
An interleaving memory system having a first memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, a second memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, and a holding device for holding data from one of the banks of one of the first memory device and the second memory device to delay an output of the data for 1/2 cycle time for sequential addressing. A controller controls first and second selection devices wherein the 0-bank and the 1-bank are alternatively selected when data is outputted either in an ascending order of consecutive addresses from the even-numbered addresses in the first or second memory devices, or in a descending order of consecutive addresses from the odd-numbered addresses in the first or second memory devices. Also, the first holding device and a bank whose output is not held by the first holding device are alternatively selected when data is outputted either in a descending order of consecutive addresses from the even-numbered addresses in the first memory device, or in an ascending order of consecutive addresses from the odd-numbered addresses in the first memory device. The second holding device and a bank whose output is not held by the second holding device are similarly alternatively selected.

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