System for handling cache memory victim data which transfers dat

Details System for handling cache memory victim data which transfers dat System for handling cache memory victim data which transfers dat

1994-06-30

1996-07-16

An, Meng-Ai

Boots, shoes, and leggings

395471, 395472, 395473, 395486, 395250, 3642398, 3642531, 3649645, 36496434, 364964342, 364DIG2, G06F 1300

Patent

active

055375758

ABSTRACT:
A method and apparatus in a computer system for handling cache memory victim data for updating main memory. The invention operates in a computer system having one or more processor modules coupled to main memory by a system bus operating in accordance with a SNOOPING bus protocol. Upon a processor executing a READ of one of the cache memory addresses, cache memory data corresponding to the cache memory address being READ is transmitted into the data interface from the cache memory data storage. The cache memory data is received accumulatively by the data interface during the execution of the READ of the cache memory address information. A determination is made as to whether the cache memory data corresponding to the cache memory address being READ is a cache memory victim. If the determination establishes that it is a cache memory victim, the processor issues a command for transmitting cache memory victim data to main memory over the system bus. In response to the command for transmitting cache memory victim data, the cache memory data which is waiting in the data interface, is transmitted from the data interface to main memory over the system bus.

REFERENCES:
patent: 4713755 (1987-12-01), Worley, Jr. et al.
patent: 4977498 (1990-12-01), Rastegar et al.
patent: 5097409 (1992-03-01), Schwartz et al.
patent: 5155832 (1992-10-01), Hunt
patent: 5206941 (1993-04-01), Eikill et al.
patent: 5319766 (1994-06-01), Thaller et al.
patent: 5353415 (1994-10-01), Wolford et al.
patent: 5404483 (1995-04-01), Stamm et al.
patent: 5426765 (1995-06-01), Stevens et al.
Tri CaoHuu; "Universal Read/Write Buffer for Multiprocessor Cache Coherency Schemes"; IEEE 1993; pp. 785-790.
Milo Tomasevic; "A survey of hardware solutions for maitenance of cache coherency in shared memory mutiprocessors"; 1993 IEEE pp. 863-872.

Affiliated with

Also associated with

Rating

System for handling cache memory victim data which transfers dat does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System for handling cache memory victim data which transfers dat, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System for handling cache memory victim data which transfers dat will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1792429