High speed CMOS FET full-adder circuit

Details High speed CMOS FET full-adder circuit High speed CMOS FET full-adder circuit

1984-05-11

1987-03-17

Malzahn, David H.

Boots, shoes, and leggings

364786, G06F 750

Patent

active

046512969

ABSTRACT:
A full-adder circuit comprising a first node for providing an inverted summed output, a second node for providing an inverted carry output, a plurality of P channel MOS FETs connected between a Vcc terminal and the first and second nodes to form a first circuit pattern, the P channel MOS FETs being applied at the gates with an addend input signal of N-bits (N is a natural number of 1 or more) and an augend input signal of N-bits, a carry input signal of one-bit, and the one-bit inverted signals of the input signals, a plurality of N channel type MOS FETs connected between a Vss terminal and the first and second nodes to form a second circuit pattern which is substantially the same as that of said first circuit pattern, said N channel type MOS FETs being applied at the gates with the same addend, augend and carry inputs as those applied to the P channel type MOS FETs in a similar manner, a first inverter connected between the first node and a summed output terminal and for inverting a signal at the first node, and a second inverter connected between the second node and a carry output terminal and for inverting a signal at the second node.

REFERENCES:
patent: 4417314 (1983-11-01), Best
patent: 4471454 (1984-09-01), Dearden et al.
patent: 4541067 (1985-09-01), Whitaker
patent: 4564921 (1986-01-01), Suganuma
Fukuma et al., "SOS CMOS 16 Bit Parallel Multiplier," 13th Conference on Solid State Devices, Tokyo 1981, pp. 15-16.

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