Exception handling circuit and method

Details Exception handling circuit and method Exception handling circuit and method

1994-02-08

1996-07-16

Treat, William M.

Boots, shoes, and leggings

364DIG1, G06F 932

Patent

active

055375596

ABSTRACT:
A microprocessor circuit monitors addresses generated by the microprocessor to check for various address-exception conditions. Fetch-exception status bits are generated for each instruction byte to indicate whether an address-exception was detected for each respective byte address. Once fetches are performed, the fetch-exception status bits are fed to an instruction buffer with the corresponding instruction bytes, where they are maintained until execution. Decode logic of an instruction control unit analyzes the fetch-exception status bits upon execution, and generates exceptions before the corresponding exception-causing instructions are executed. Address-exceptions occurring as the result of operand accesses are handled immediately. The operand access causing the exception is aborted, and the decode of the following instruction is modified to generate a micro-interrupt. A micro-interrupt routine determines the cause of the interrupt, and generates the appropriate exception. For breakpoint exceptions on operand accesses, the micro-interrupt routine re-executes the breakpoint-causing instruction to completion before generating the appropriate exception.

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