Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

1985-10-17

1987-03-17

Wojciechowicz, Edward J.

357 231, 357 41, 357 42, H01L 2710

Patent

active

046511903

ABSTRACT:
A semiconductor integrated circuit includes p- and n-type semiconductor areas alternately arranged in a row direction, p-channel MOS transistor blocks arranged in each of the p-type semiconductor areas and each including two p-channel MOS transistors, n-channel MOS transistor blocks arranged in each of the n-type semiconductor areas and each including two n-channel MOS transistors, and p- and n-type diffusion areas formed, respectively, in each of the p-type semiconductor areas and in each of the n-type semiconductor areas. The MOS transistor blocks are arranged on two columns in each of the p- and n-type semiconductor areas, and each of the diffusion areas is formed in a position defined by the gate electrodes of four MOS transistors of the same channel type in the two MOS transistor blocks adjacent to each other in a row direction.

REFERENCES:
patent: 4288804 (1986-03-01), Kikuchi et al.
patent: 4516312 (1985-05-01), Tomita
Bansal-IBM Tech. Bul.-vol. 26, No. 5, Oct. 1983, pp. 2404-2407, "CMOS (N-Well) Master Image Chip".
Takechi et al., "A CMOS 12K-Gate Array With Flexible 10KB Memory", IEEE International Solid-State Circuits Conference, ISSCC Digest of Technical Papers, pp. 258-259, Feb. 24, 1984.

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