Synchronous DRAM tester

Details Synchronous DRAM tester Synchronous DRAM tester

1995-04-28

1996-10-29

Beausoliel, Jr., Robert W.

Excavating

365201, 395550, 371 211, G11B 2700, H03M 1300, H04L 700

Patent

active

055703810

ABSTRACT:
A method of testing synchronous dynamic random access memories (SDRAMs) having a pair of memory banks, comprised of writing data into a first of the pair of memory banks at a first clock speed that can be used by a tester, transferring the data at a second clock speed much higher than the first clock speed from the first of the pair of memory banks to a second of the pair of memory banks, and then reading the second of the pair of memory banks at the first clock speed to the tester.

REFERENCES:
patent: 5265049 (1993-11-01), Takasugi
patent: 5394399 (1995-02-01), Kawasaki et al.
patent: 5414816 (1995-05-01), Oyadomari
patent: 5495585 (1996-02-01), Datwyler et al.

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