Scan test

Details Scan test Scan test

1995-08-24

1998-02-17

Nguyen, Hoa T.

Excavating

G01R 3178

Patent

active

057198772

ABSTRACT:
A method of testing the performance of a combinational logic circuit is described. In contrast to a structural test which verifies the operation of the combinational logic circuitry, a performance test allows the performance of a combinational logic circuit to be tested by determining the accuracy of a set of outputs resulting from a change in input bits to the combinational logic circuit. Thus, it is possible to monitor more closely performance aspects, such as the maximum delay from input to output of a combination logic circuit.

REFERENCES:
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patent: 5130568 (1992-07-01), Miller et al.
Proceedings of the IEEE 1992 Custom Integrated Circuits Conference, May 3, 1992, Boston, MA USA pp. 13.2.1-13.2.4, H. Chang et al. "Delay Test Techniques for Boundary Scan Based Architectures".
Computer Design, vol. 32, No. 10, Oct. 1993, Westford, MA, USA, pp. 69-72, P. Varma "Timing Driven Test --From Chips To Systems".
Proceedings of the 1991 International Test Conference, pp. 365-374, B.I. Dervisoglu "Design For Testability: Using Scanpath Techniques for Path-Delay Test and Measurement".
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 11, No. 7, Jul. 1992, New York, US pp. 926-938, E.S. Park, et al. "An Efficient Delay Test Generation System for Combinational Logic Circuits".

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