Scan latch using half latches

Details Scan latch using half latches Scan latch using half latches

1995-08-24

1998-02-17

Nguyen, Hoa T.

Excavating

371 211, 371 221, G01R 3128

Patent

active

057198764

ABSTRACT:
A scan latch is described which comprises a capture half-latch, a release half-latch and an update half-latch. The capture half-latch has an input terminal connected to receive an input signal, a control terminal connected to a clock signal, and an output terminal. The release half-latch and update half latch each have an input terminal fixedly connected to the output terminal of the capture half latch. The release half-latch also has a control terminal connected to a clock signal and an scan output terminal. The update half-latch also has a control terminal connected to a clock signal and a data output terminal. The combination of the capture half-latch and one of the update half-latch and the release half-latch acts as a full-latch. The combination of these half-latches allows for simplified circuitry for testing integrated circuits. Clock signals provided to the half-latches can be different clock signals, and their timing can be individually controlled. This scan latch comprising half-latches can be used in place of any full-latch where a scan test is to be carried out and where a functional data output should not change while scan data is being shifted in or out. Furthermore, a scan latch according to this invention is also able to carry out a performance test to test the timing of logic circuitry. A method of using the scan latch to carry out a structural test of a circuit is also described.

REFERENCES:
patent: 4697279 (1987-09-01), Baratti et al.
patent: 4742293 (1988-05-01), Koo et al.
patent: 5015875 (1991-05-01), Giles et al.
patent: 5130568 (1992-07-01), Miller et al.
patent: 5281864 (1994-01-01), Haln et al.
Proceedings of the IEEE 1992 Custom Integrated Circuits Conference, May 3, 1992, Boston, MA, USA pp. 13.2.1-13.2.4, H. Chang, et al. "Delay Test Techniques For Boundary Scan Based Architectures".
Proceedings of the 12th IEEE VLSI Test Symposium, Apr. 25, 1994, Cherry Hill, N.J., USA, pp. 284-290 J. Savir, et al. "On Broad-Side Delay Test".

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