Separate byte control on fully synchronous pipelined SRAM

Details Separate byte control on fully synchronous pipelined SRAM Separate byte control on fully synchronous pipelined SRAM

1999-05-26

2000-06-27

Zarabian, A.

Static information storage and retrieval

Addressing

Sync/clocking

36518912, G11C 800

Patent

active

060814780

ABSTRACT:
A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. The logic circuit also detects which bytes of data are not to be written into the SRAM so that, during a read operation, those bytes not to be written into the SRAM are read from the SRAM in order to output a complete word corresponding to the value at the read address.

REFERENCES:
patent: 4882709 (1989-11-01), Wyland
patent: 5515325 (1996-05-01), Wada
patent: 5526320 (1996-06-01), Zagar et al.
patent: 5546344 (1996-08-01), Fawcett
patent: 5568430 (1996-10-01), Ting
patent: 5577236 (1996-11-01), Johnson et al.
patent: 5617362 (1997-04-01), Mori et al.
patent: 5644729 (1997-07-01), Amini et al.
patent: 5652724 (1997-07-01), Manning
patent: 5659696 (1997-08-01), Amini et al.
patent: 5663901 (1997-09-01), Wallace et al.
patent: 5675549 (1997-10-01), Ong et al.
patent: 5699317 (1997-12-01), Sartore et al.
patent: 5828606 (1998-10-01), Mick
patent: 5838631 (1998-11-01), Mick
patent: 5841732 (1998-11-01), Mick
patent: 5875151 (1999-02-01), Mick
Prince, Betty, Semiconductor Memories, Second Edition, 467-472 (John Wiley & Sons ed., 1991)(1983).

Affiliated with

Also associated with

Rating

Separate byte control on fully synchronous pipelined SRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Separate byte control on fully synchronous pipelined SRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Separate byte control on fully synchronous pipelined SRAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1789818