Boots – shoes – and leggings
Patent
1992-10-22
1994-11-08
Ray, Gopal C.
Boots, shoes, and leggings
395250, 3642402, 3642403, 3642328, 364239, 364DIG1, G06F 1340, G06F 1300
Patent
active
053634942
ABSTRACT:
A first bus wiring line to which a plurality of first circuits each having the same bit range are connected, a second bus wiring line to which a plurality of second circuits each having a bit range smaller than that of each of the first circuits are connected, and a bus interface circuit having a buffer circuit connected between a portion of the first bus wiring line and the second bus wiring line and a dummy buffer circuit connected to the remaining portion of the first bus wiring line are arranged in an integrated circuit. Fox this reason, when a plurality of circuits having different bit ranges are connected to the bus wiring lines, the loads of the bus wiring lines can be made uniform, and a data transfer operation through the bus lines can be performed at a high speed. The operating frequency of a clock can be increased, and the performance of the system can be improved.
REFERENCES:
patent: 4683534 (1987-07-01), Tietjen et al.
patent: 5113369 (1992-05-01), Kijnoshita
patent: 5131083 (1992-07-01), Crawford et al.
patent: 5148539 (1992-09-01), Enomoto et al.
patent: 5191653 (1993-03-01), Banks et al.
patent: 5255374 (1993-10-01), Aldereguia et al.
patent: 5274763 (1993-12-01), Banks
patent: 5274795 (1993-12-01), Vachon
Kabushika Kaisha Toshiba
Ray Gopal C.
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