Semiconductor storage circuit device operating in a plurality of

Details Semiconductor storage circuit device operating in a plurality of Semiconductor storage circuit device operating in a plurality of

1996-07-11

1998-02-17

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523005, G11C 800

Patent

active

057198195

ABSTRACT:
It is an object to enable access orders for a memory circuit used in the digital image compression technology only with counting-up operation by a counter circuit. The correspondence between outputs of first and second decoders (4, 5) forming a two-port RAM (3) is made different according to two operation modes. That is to say, while outputs 0, 1, 2, . . . , 63 of the first decoder (4) are arranged corresponding to an access order of increment, outputs 0, 1, 2, . . . , 63 of the second decoder (5) are arranged in correspondence with the outputs of the first decoder (4) on the basis of an access order in the zig-zag scan, here. An address generating circuit (7) as a counter circuit supplies common addresses to the two decoders (4, 5). Thus, while the two-port memory cells are respectively accessed in the increment order by outputs of the first decoder (4), they are also accessed in the operation mode for the zig-zag scan by outputs of the second decoder (5).

REFERENCES:
patent: 5235552 (1993-08-01), Nakajima et al.
patent: 5293347 (1994-03-01), Ogawa
patent: 5321652 (1994-06-01), Ito
patent: 5434818 (1995-07-01), Byers et al.
patent: 5490112 (1996-02-01), Hush et al.
patent: 5566371 (1996-10-01), Ogawa
patent: 5602778 (1997-02-01), Futatsuya et al.

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