High speed addition using Ling's equations and dynamic CMOS logi

Details High speed addition using Ling's equations and dynamic CMOS logi High speed addition using Ling's equations and dynamic CMOS logi

1996-05-31

1998-02-17

Mai, Tan V.

Boots, shoes, and leggings

36478405, G06F 750

Patent

active

057198039

ABSTRACT:
The methods and apparatus disclosed allow for a direct implementation of Ling's equations in a dynamic CMOS logic environment. In summary, low order Ling pseudo-carries and group propagate terms are generated in parallel in a single gate delay. After generating low order terms, local and non-local carry propagation proceed in parallel. Local carry propagation occurs within each quadrant of an adder and comprises 1) a dual carry ripple between most significant bits of a quadrant's low order groups, and 2) dual carry ripples between less significant bits of a quadrant's low order groups. Missing terms in low order Ling pseudo-carries and propagate terms are reabsorbed during the dual carry ripples. Non-local carry propagation first involves combining low order group terms to form 1) Ling pseudo-carries out of quadrants, and 2) quadrant-wide propagate terms. This occurs during a single gate delay. Quadrant terms are then used to generate long carries which may be used in selecting the appropriate carries, and hence, the appropriate sum, for each quadrant. Long carry generation also occurs in a single gate delay. Finally, a sum is generated and selected during a fourth and final gate delay. Circuit modularity provides for logical reductions in transistor count, and a dense layout. The disclosed adder's implementation of Ling's equations in a dynamic CMOS environment (with early reabsorption of missing propagate terms) enables construction of a 64 bit adder having a mere four gate delays between operand input and sum output.

REFERENCES:
patent: 4569032 (1986-02-01), Lee
patent: 4858168 (1989-08-01), Hwang
patent: 4899305 (1990-02-01), Needles
patent: 5140546 (1992-08-01), Ishikawa et al.
patent: 5208490 (1993-05-01), Yetter
patent: 5285406 (1994-02-01), Lynch et al.
patent: 5329477 (1994-07-01), Kudou
patent: 5392423 (1995-02-01), Yetter
patent: 5581497 (1996-12-01), Kumar
N. Quach & M. Flynn, "High Speed Addition in CMOS", Stanford Technical Rep.: CSL-TR-90-415, Feb. 1990.
M. Flynn, "Topics in Arithmetic For Digital Systems Designers" (Preliminary Second Edition .sctn.1992), pp. 89-94, 102-105.
H. Ling, "High Spped Binary Adder", IBM J. of Res. & Dev., vol. 25, No. 3, pp. 156-166, May 1981.
H. Ling, "High Speed Binary Parallel Adder", IEEE Trans. Comput., pp. 799-802, Oct. 1966.
Dobberpuhl et al., "A 200-Mhz 64b Dual-Issue CMOS Microprocessor", IEEE J. of Solid State Circuits, vol. 27, No. 11, pp. 1555-1567, Nov. 1992.
A. Inoue, Y. Kawabe, Y.Asada & S. Ando, "A 0.4} m 1.4ns 32b Dynamic Adder using Non-precharge Multiplexers and Reduced Precharge Voltage Technique", Symp. VLSI Circuits Digest of Tech. Papers, pp. 9-10, Jun. 1995.
M. Suzuki et al., "A 1.5-ns 32-b CMOS ALU in Double Pass-Transistor Logic" IEEE J. of Solid State Circuits, vol. 28, No. 11, pp. 1145-1151, Nov. 1993 .

Affiliated with

Also associated with

Rating

High speed addition using Ling's equations and dynamic CMOS logi does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed addition using Ling's equations and dynamic CMOS logi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed addition using Ling's equations and dynamic CMOS logi will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1789277