Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Patent
1998-03-09
2000-06-27
Picard, Leo P.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
257390, 257295, 257305, 257775, 257767, 257310, H01L 23528, H01L 23535
Patent
active
06081036&
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a semiconductor device and, more particularly, to a construction for suppressing deterioration of performance and reliability due to thermal stresses that are generated in its composing material.
BACKGROUND ART
Conventionally, there is a semiconductor device which has a multilayer wiring structure. In such a semiconductor device, lower layer wirings and upper layer wirings are electrically connected through contact holes that are formed in an interlayer insulating film.
FIG. 13 is a diagram for explaining a wiring structure of such a semiconductor device. FIG. 13(a) is a plan view, and FIG. 13(b) is a cross-sectional view along a line XIIIb--XIIIb shown in FIG. 13(a). In the figure, reference numeral 250 designates a wiring structure that is formed on a silicon substrate 5. This wiring structure 250 has a lower layer wiring (first wiring) 1 that extends along a first direction D1 and has a wiring width direction in a second direction D2 perpendicular to the first direction D1, and upper layer wirings (second wirings) 2a and 2b that extend along the first direction D1 and are electrically connected to the lower layer wiring 1.
More specifically, the lower layer wiring 1 is formed on the silicon substrate 5 via an underlying insulating film 6, and the lower layer wiring 1 is covered with an interlayer insulating film 7. Further, the upper layer wirings (second wirings) 2a and 2b are formed on the interlayer insulating film 7. An end portion 2a.sub.1 of the upper layer wiring 2a is connected to an end portion 1a of the lower layer wiring 1 through a contact hole 7a that is formed in the interlayer insulating film 7. An end portion 2b.sub.1 of the upper layer wiring 2b is connected to the other end portion 1b of the lower layer wiring 1 through a contact hole 7b that is formed in the interlayer insulating film 7.
As a composing material of the upper layer wirings 2a and 2b, a metallic material of a low melting point, such as aluminum, which is relatively low-priced is used. As a composing material of the lower layer wiring 1, a metallic material of a high melting point, such as platinum and tungsten, is used, because various high temperature processing is usually performed after formation of the lower layer wiring.
By the way, as the conventional semiconductor devices having multilayer wiring structures described above, there have been developed various circuits from relatively small-sized integrated circuits mounting, for example, an amplifier circuit, an oscillating circuit, a power supply circuit and the like, to relatively large-sized integrated circuits, such as a microprocessor and a memory device. Especially in recent years, as a kind of non-volatile memory device, a ferroelectric memory device with ferroelectric capacitors as capacitors constituting memory cells has been contrived.
The ferroelectric capacitor consists of a pair of electrodes opposite to each other, and a dielectric layer comprising a ferroelectric material and sandwiched between both electrodes, and has the hysteresis characteristic as a relationship between a voltage applied between the both electrodes and polarizability of the ferroelectric material. That is, the ferroelectric capacitor has a construction in which even when the electric field (applied voltage) is zero, a remanence of a polarity in accordance with the hysteresis of voltage application remains in the ferroelectric layer. In the ferroelectric memory device non-volatility of the storage data is realized by representing storage data by the remanence of the ferroelectric capacitor.
FIGS. 14 and 15 are diagrams for explaining a conventional ferroelectric memory device. FIG. 14 is a plan view illustrating a memory cell array in the ferroelectric memory device. FIG. 15(a) is a cross-sectional view of a part along a line XVa--XVa shown in FIG. 14, FIG. 15(b) is a cross-sectional view of a part along a line XVb--XVb shown in FIG. 14, and FIG. 15(c) is a cross-sectional view of a part along a line XVc--XVc shown in FIG. 14.
In
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Hirano Hiroshige
Honda Toshiyuki
Duong Hung Van
Matsushita Electronics Corp.
Picard Leo P.
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