Extended duration high resolution timer contained in two integra

Details Extended duration high resolution timer contained in two integra Extended duration high resolution timer contained in two integra

1992-10-02

1995-10-31

Kriess, Kevin A.

Boots, shoes, and leggings

3642464, 364270, 3642701, 3642703, G06F 100

Patent

active

054637619

ABSTRACT:
A computer system provides a 48-bit timer having 120 ns resolution and possessing a rollover period in excess of one year. The preferred embodiment includes two system data buffers (SDBs), each of which includes a full 48-bit timer. The timers are synchronized, and the output of each timer is provided to the host bus in alternating pairs of bits, so that half of the data bits are provided by the first SDB and half of the timer bits are provided by the second SDB. The timer may be read either as a 48-bit timer or a 32-bit timer.

REFERENCES:
patent: 4040022 (1977-08-01), Takii
patent: 4201337 (1980-05-01), Lewis et al.
patent: 4993028 (1991-02-01), Hillis
patent: 5119486 (1992-06-01), Albonesi
patent: 5206865 (1993-04-01), Gruender, Jr. et al.
Wortzman, D., "Two Tier Error Correcting Code for Memories", IBM Technical Disclosure Bulletin, vol. 26, No. 1 OA, Mar. 1984, pp. 5314-5318.
Rao, T. et al., Error-Control Coding for Computer Systems, Prentice-Hall, 1988, pp. 221-298.
D. C. Bossen, B-Adjacent Error Connection, IBM J. Res. Develop., Jul. 1970 pp. 402-408.

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