Instruction buffer controller in processor enabling direct refet

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Details

36424341, 364DIG1, 364DIG2, 395375, 39542103, G06F 1200

Patent

active

054637376

ABSTRACT:
An instruction buffer controller according to the present invention comprises an instruction buffer for prefetching and writing of instructions in the main storage and a storage pointer which holds the address of the instruction fetched from the instruction buffer currently being executed or initial addresses of completed instructions in the instruction buffer. It also comprises a storage controller which stores the instruction currently being executed at the instruction buffer until execution completion of that instruction or stores a predetermined number of completed instructions at the instruction buffer. It causes its judgment means to judge whether the address of the instruction to be re-fetched exists between the writing address for the instruction buffer and the storage pointer address and, if such address exists there, sets the address of the re-fetched instruction at the reading pointer as the reading address of the instruction buffer.

REFERENCES:
patent: 4442488 (1984-04-01), Hall
patent: 5185871 (1993-02-01), Frey et al.
patent: 5285527 (1994-02-01), Crick et al.
patent: 5317720 (1994-05-01), Stamm et al.

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