Reduced quantization noise from single-precision multiplier

Details Reduced quantization noise from single-precision multiplier Reduced quantization noise from single-precision multiplier

1994-06-24

1995-10-31

Envall, Jr., Roy N.

Boots, shoes, and leggings

364745, G06F 738, G06F 752

Patent

active

054635756

ABSTRACT:
A single-precision multiplier used in a recursive digital filter is rendered more precise, without resorting to extended-precision or floating-point arithmetic. A double-precision multiplier produces a group of most significant bits (MSBs) and a group of least significant bits (LSBs). The LSBs are processed, including delaying them by one or two clock cycles, and are then added back to the LSBs produced during the present clock cycle. The top few bits of this first sum are right shifted as far as possible and added to the MSBs, the resulting second sum being the output of the overall multiplier.

REFERENCES:
patent: 4229800 (1980-10-01), Gregorian et al.
patent: 5128889 (1992-07-01), Nakano
patent: 5276634 (1994-01-01), Suzuki
patent: 5329475 (1994-07-01), Juri et al.
patent: 5341319 (1994-08-01), Madden et al.

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