Method for fabricating stacked CMOS transistors with a self-alig

Details Method for fabricating stacked CMOS transistors with a self-alig Method for fabricating stacked CMOS transistors with a self-alig

1985-08-05

1987-04-14

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29571, 29591, 148 15, 148175, 148187, 357 42, 357 234, 357 237, 357 91, H01L 2188, H01L 2978, H01L 2702

Patent

active

046567313

ABSTRACT:
A method for siliciding interconnects on a vertically integrated device utilizing stacked CMOS technology includes a step for blocking off the p-channel devices. This blocking step is utilized to block the p-channel device in a stacked CMOS pair prior to forming titanium di-silicide on the exposed polysilicon interconnects. A mask is formed on the top polysilicon layer that forms the p-channel device and then patterned to remove the mask and the top polysilicon layer to expose the underlying polysilicon layers. A sidewall oxide is then formed to completely seal the p-channel devices and then the exposed silicon and polysilicon surfaces subjected to a self-aligned silicide process.

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Alperin et al, IEEE-Trans. Electron Devices, ED32 (1985) 141.
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