System for multiple error detection with single and double bit e

Details System for multiple error detection with single and double bit e System for multiple error detection with single and double bit e

1984-01-26

1986-05-13

Atkinson, Charles E.

Excavating

371 39, G06F 1110

Patent

active

045891125

ABSTRACT:
A system for detecting multiple errors that may occur during transfer of data and for correcting up to two of these errors simultaneously. The system has a component for calculating a number of check bits associated with the data word. Also provided is a component for grouping all data bits into base groups and multiple groups, the sum of the number of base groups and multiple groups being equal to the number of check bits. Up to two weights are assigned for each data bit. The system distributes the data bits among the groups according to the weights assigned thereto. Also provided is a component for generating a check bit for each of the groups and for padding the data word with the check bits to form an appended data word. A generator creates a predetermined number of syndrome bits, the number being the number of check bits. Finally, a decoder is provided for decoding the syndrome bits to identify the erroneous bits in the data word.

REFERENCES:
patent: 3622982 (1971-11-01), Clark, Jr. et al.
patent: 3685014 (1972-08-01), Hsiao et al.
patent: 3714629 (1973-01-01), Hong et al.
patent: 4030067 (1977-06-01), Howell et al.
patent: 4117458 (1978-09-01), Burghard et al.

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