Solid slice memory

Details Solid slice memory Solid slice memory

1982-12-20

1986-05-13

Moffitt, James W.

Static information storage and retrieval

Addressing

365189, G11C 700

Patent

active

045890994

ABSTRACT:
An electronic system located upon a single semiconductor substrate including a plurality of isolated electronic subsystems located upon the semiconductor substrate. Each electronic subsystem includes a plurality of input/output lines. Several information bus lines are included that are connected to addressable transistors located between the individual bus lines and the input/output lines. An addressing means is connected to the addressable transistors for addressing each of the addressable transistors and for providing a first state signal indicating an ON condition to the first select group of said addressable transistors, electrically connecting the information bus lines to the input/output lines and a second state signal indicating an OFF condition to a second selected group of the addressable transistors, electrically isolating the information bus lines from the input/output lines. The addressable transistors maintain the state signal indicated condition.

REFERENCES:
patent: 4472792 (1984-09-01), Shimohigashi et al.

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