Semiconductor device having interconnection layers of T-shape cr

Details Semiconductor device having interconnection layers of T-shape cr Semiconductor device having interconnection layers of T-shape cr

1988-01-13

1990-02-27

James, Andrew J.

357 236, 357 54, 357 71, H01L 2348

Patent

active

049050680

ABSTRACT:
A cell plate (6) is formed on a main surface of a semiconductor substrate (7) with an insulating film (8) interposed therebetween and an interconnection (1) having T-shape cross section is formed on the cell plate (6) with an interlayer insulating film (11) interposed therebetween. An upper insulating film (12) is formed to cover the interconnection (1).

REFERENCES:
patent: 4476959 (1988-05-01), Mueller
patent: 4488166 (1984-12-01), Lehrer
patent: 4617193 (1986-10-01), Wu
F. Mohammadi "Silicides for Interconnection Technology" Solid State Technology (Jan. 1981), pp. 65-72, 92.
D. S. Yaney et al., "Technology for the Fabrication of A 1 MB CMOS DRAM" IEDM 1985 (1985), pp. 698-701.
E. T. Lewis "An Analysis of Interconnect Line Capacitance and Coupling for VLSI-Circuits" Solid-State Electronics, vol. 27, Nos. 8/9, pp. 741-749 (1984).
J. Summers "Interconnecting High Speed Logic" Electronic Engineering (Mar. 1985), pp. 133-140.

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