Digital waveform conditioning circuit

Details Digital waveform conditioning circuit Digital waveform conditioning circuit

1985-02-08

1986-05-13

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307268, 307352, 307358, 307603, 328162, H03K 513, H03K 1200, H03K 5153

Patent

active

045889058

ABSTRACT:
A digital waveform conditioning circuit for restoring a deformed digital signal into its original rectangular waveform, comprising an input terminal supplied with the deformed digital signal, a circuit for generating a reference signal by combining positive and negative voltage components rectified from positive and negative cycles of the deformed signal, a comparator for comparing the deformed signal with the reference signal, a circuit for holding an output signal of the comparator for a period controlled by a clock signal for synchronizing the output signal with the original rectangular signal, and an output terminal for receiving the output of the holding circuit.

REFERENCES:
patent: 3239694 (1966-03-01), Rovell
patent: 3375450 (1968-03-01), Ayres et al.
patent: 3473131 (1969-10-01), Perkins
patent: 3584310 (1971-06-01), Hochfelder
patent: 3708678 (1973-02-01), Kreda
patent: 3772604 (1973-11-01), Hogg et al.
patent: 4241455 (1980-12-01), Eibner
patent: 4281317 (1981-07-01), Pace
patent: 4406988 (1983-09-01), Scholz
Translation of Spring.
Viles, "Upper & Lower Thresholds Can Be Set Independently in Latching-Comparator Circuit", Electronic Design, 12/30/77.
Analog and Digital Communication, pp. xvii and 387, 388, 389, 1977, W. David Gregg, John Wiley & Sons, New York.

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