Integrated injection logic with both grid and internal double-di

Details Integrated injection logic with both grid and internal double-di Integrated injection logic with both grid and internal double-di

1977-07-14

1978-10-10

Larkins, William D.

357 46, 357 50, H01L 2704

Patent

active

041199987

ABSTRACT:
An integrated injection logic semiconductor device is composed of an N type semiconductor substrate, a P type layer, a first N type region so formed as to penetrate through the P type semiconductor layer and contact the N type semiconductor substrate, a second N type region formed in the P type semiconductor layer, and a P type region formed in the first N type region. A third N type region is provided surrounding said first and second N type regions and penetrating through the P type semiconductor layer. I.sup.2 L circuit is composed of a lateral PNP transistor whose emitter, base and collector are constituted by said P type region, said first N type region and said P type semiconductor layer, respectively, and a vertical NPN transistor whose emitter, base and collector are constituted by said N type semiconductor substrate, said P type semiconductor layer and said second N type region, respectively.

REFERENCES:
patent: 3823353 (1974-07-01), Berger et al.
patent: 3922565 (1975-11-01), Berger et al.
patent: 3947865 (1976-03-01), Russell
patent: 3982266 (1976-09-01), Matzen et al.
patent: 4056810 (1977-11-01), Hart et al.

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