Floating point processor with high speed rounding circuit

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Details

364748, G06F 1100, G06F 738

Patent

active

052893960

ABSTRACT:
In a data processor, second data are subtracted from first data to derive an overflow signal. The sum of the second data and "1" is subtracted from the first data to derive another overflow signal. The magnitude relation between the first and second data from the overflow signals is detected.

REFERENCES:
patent: 3814925 (1974-06-01), Spannagel
patent: 4075704 (1978-02-01), O'Leary
patent: 4218751 (1980-08-01), McManigal
patent: 4562553 (1985-12-01), Mattedi et al.
patent: 4592006 (1986-05-01), Hagiwara et al.
patent: 4644490 (1987-02-01), Kobayashi et al.
patent: 4779220 (1988-10-01), Nukiyama
patent: 4807172 (1989-02-01), Nukiyama
patent: 4841467 (1989-06-01), Ho et al.
patent: 4849921 (1989-07-01), Yasumoto et al.
patent: 4858165 (1989-08-01), Gronowski et al.
patent: 4888722 (1989-12-01), Boreland
patent: 5117384 (1992-05-01), Drehmel et al.

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