Methods for metal etching with reduced sidewall build up during

Details Methods for metal etching with reduced sidewall build up during Methods for metal etching with reduced sidewall build up during

1997-06-20

1998-12-08

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438712, 438738, H01L 2100

Patent

active

058468846

ABSTRACT:
A method in a plasma processing chamber for etching through a selected portion of a layer stack. The layer stack comprises a metallization layer, a first barrier layer disposed adjacent to the metallization layer, and a photoresist layer disposed above the metallization layer. The method includes etching at least partially through the first barrier layer using a high sputter component etch. The method further includes etching at least partially through the metallization layer using a low sputter component etch. The low sputter component etch has a sputter component lower than a sputter component of the high sputter component etch.

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