Voltage-to-charge transducer

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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357 24, G11C 1928, H01L 2978

Patent

active

042464960

ABSTRACT:
A voltage-to-charge transducer utilizing a capacitor circuit is provided to generate whole or fractional charge packets at spaced apart locations in a semi-conductor substrate. Each of a pair of conductive lines connected to opposite sides of the capacitor circuit is selectively precharged to a predetermined voltage value by means of one of a pair of charge transfer devices coupled to the input of first and second charge coupled device (CCD) storage systems. Means are also provided for applying voltages of first and second magnitudes to each of the pair of conductive lines. By precharging one of the pair of conductive lines to the predetermined voltage value and by altering the voltage on the other of the pair of conductive lines from the first magnitude to the second magnitude, a first charge packet is formed in a well of the first CCD storage system. To inject a duplicate of the first packet into a well of the second CCD storage system, similar voltages are established across the capacitor circuit relative to the second CCD storage system. To inject into the second CCD storage system a charge packet which is a fraction of the first packet, the similar voltages differ only in that the voltage difference between the first and second magnitudes is altered to a fraction equal to the fraction of the desired fractional charge packet. By precharging the conductive lines coupled to the capacitor circuit, parasitic effects are neutralized or eliminated in the transducer.

REFERENCES:
patent: 3656011 (1972-04-01), Weinberg
patent: 3902186 (1975-08-01), Engeler et al.
patent: 4035667 (1977-07-01), Heller
patent: 4047051 (1977-09-01), Heller
patent: 4085459 (1978-04-01), Hirabayashi
Jespers et al., "A Fast Sample and Hold Charge-Sensing Circuit for Photodiode Arrays" IEEE J. Solid-State Circuits vol. SC-12 (6/77) pp. 232-237.
Lee, "Converter for CCD Multilevel Shift Registers" IBM Technical Disclosure Bulletin vol. 20 (1/78) pp. 3011-3013.
Hiltebeitel et al., "Fractional Charge Packet Generator" IBM Technical Disclosure Bulletin vol. 20 (1/78) pp. 3014-3016.

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