System for method memory error handling

Details System for method memory error handling System for method memory error handling

1996-11-01

1999-05-18

Beausoliel, Jr., Robert W.

Excavating

39518203, 39518318, 371 401, G06F11/08

Patent

active

059058587

ABSTRACT:
A computer system stores data according to a plurality of different error handling schemes. The computer system includes a memory controller with a plurality of different error handling modules, each of which can be selectively associated with one or more memory blocks. Each of the error handling modules is structured to write data to and read data from its associated memory block according to a different error handling scheme. A memory controller includes a separate configuration register for each of the plurality of memory blocks. Each configuration register stores an indication of the error handling module that will be employed to write data to and read data from the memory block associated with the configuration register.

REFERENCES:
patent: 3668644 (1972-06-01), Looschen
patent: 5499384 (1996-03-01), Lentz et al.
patent: 5550988 (1996-08-01), Sarangdhar et al.
patent: 5588112 (1996-12-01), Dearth et al.
patent: 5604753 (1997-02-01), Bauer et al.

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