Test circuit

Details Test circuit Test circuit

1997-01-27

1999-05-18

Beausoliel, Jr., Robert W.

Excavating

365201, G01R21/28

Patent

active

059057378

ABSTRACT:
In a normal mode, a logic test signal (LOGTEST), a RAM test signal (RAMTEST), and a shift mode signal (SM) are set to "0". A RAM core (91) is synchronously written and asynchronously read. In a logic test mode, the RAM test signal (RAMTEST) is set to "0", and the logic test signal (LOGTEST) is set to "1". In a RAM test mode, the RAM test signal (RAMTEST) is set to "1", and the logic test signal (LOGTEST) is set to "0". A scan path (3a) is used both as a scan path provided between logic portions (82, 83) in the logic test and as a scan path provided at the output of the RAM core (91) in the RAM test. The scan path provides a high area utilization efficiency.

REFERENCES:
patent: 4503537 (1985-03-01), McAnney
patent: 5155432 (1992-10-01), Mahoney
patent: 5257267 (1993-10-01), Ishizaka
patent: 5260949 (1993-11-01), Hashizume et al.
patent: 5428622 (1995-06-01), Kuban et al.
patent: 5448575 (1995-09-01), Hashizume
patent: 5459736 (1995-10-01), Nakamura
patent: 5471481 (1995-11-01), Okumoto et al.
patent: 5592493 (1997-01-01), Cruoch et al.
patent: 5631911 (1997-05-01), Whetsel, Jr.

Affiliated with

Also associated with

Rating

Test circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1765727