Method of forming planar isolation regions having field inversio

Details Method of forming planar isolation regions having field inversio Method of forming planar isolation regions having field inversio

1982-06-03

1984-09-25

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 148 15, 148187, 357 91, H01L 21263, H01L 21225, H01L 754

Patent

active

044728743

ABSTRACT:
A method for manufacturing integrated circuit devices wherein semiconductor elements are isolated by insulation material comprising the following steps of: (a) providing a mask pattern on a predetermined semiconductor element region of a semiconductor substrate; (b) introducing by first ion-implantation impurities of the same conductivity type as that of the substrate into the substrate using the mask pattern as an ion-implantation mask; (c) etching the substrate and forming a groove using the mask pattern as an etching mask in a manner that part of the impurities remain at least under the mask pattern in the side walls of the groove; (d) introducing by second ion-implantation impurities of the same conductivity type as that of the substrate through the groove into the substrate; (e) burying insulation material in the groove; and (f) forming a semiconductor element on the predetermined semiconductor element region.

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patent: 4218267 (1980-08-01), Maddox, Jr.
patent: 4354307 (1982-10-01), Vinson et al.
patent: 4356042 (1982-10-01), Gedaly et al.
patent: 4373965 (1983-02-01), Smigelski
patent: 4385947 (1983-05-01), Halfacre et al.

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