Data processing unit with a TLB purge function

Details Data processing unit with a TLB purge function Data processing unit with a TLB purge function

1984-10-24

1989-07-18

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 922, G06F 1210

Patent

active

048498815

ABSTRACT:
A data processing unit with a TLB purge function has an address counter in which TLB purge data including an address space identifier, segment number, and page number are held. In TLB purge processing, A TLB is indexed by the upper data from the counter so that for the contents of the corresponding entry, an upper address space identifier, an upper segment number, an upper page number, and a valid flag are connected to a TLB hit detector. The lower data from the counter and three mask bits of a nano-instruction are also connected to the TLB hit detector. The TLB hit detector includes three comparators which compare the upper address space identifiers, the upper segment numbers, and the upper page numbers, which are respectively derived from the counter and the TLB. The result of each comparison and a mask bit are ORed. The ORed signal and the valid flag are supplied to an AND gate, thereby checking whether the TLB hit is present or not. When the TLB hit is detected, a write clock signal is generated, and the valid flag of the corresponding entry in the TLB is reset. The counter is incremented when the unit is operated in any mode other than single purge mode. The incrementing continues until the bits in that field of the counter which corresponds to a specified TLB purge processing mode are all 1's.

REFERENCES:
patent: 4004278 (1977-01-01), Nagashima
patent: 4068303 (1978-01-01), Morita
patent: 4145738 (1979-03-01), Inoue et al.
patent: 4400774 (1983-08-01), Toy
patent: 4467414 (1984-08-01), Akagi et al.
patent: 4481573 (1984-11-01), Fukunaga et al.
patent: 4654777 (1987-03-01), Nakamura

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