Method for handling an overflow condition in a processor

Details Method for handling an overflow condition in a processor Method for handling an overflow condition in a processor

1997-06-23

1999-05-18

Mai, Tan V.

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G06F7/38

Patent

active

059056614

ABSTRACT:
A method for handling an overflow condition in a processor is disclosed. A first plurality of signal data is packed into a first memory location so as to form a first word. A second plurality of signal data is packed into a second memory location so as to form a second word. A bitwise operation is then performed between the first word and the second word to produce a result. The result of the operation is then stored in a k bit memory location so as to form a third word. The third word is then shifted left (k-9) bits. A bit mask is then obtained by arithmetic shifting the third word right (k-1) bits. A logical OR operation is then performed between the bit mask and the result.

REFERENCES:
patent: 5197022 (1993-03-01), Ushiki et al.
patent: 5497340 (1996-03-01), Uramoto et al.
patent: 5508951 (1996-04-01), Ishikawa
patent: 5606677 (1997-02-01), Balmer et al.
"The UltraSPARC Processor--Technology White Paper; The UltraSPARC Architecture," Nov. 14, 1995, Sun Microsystems, Inc., Palo Alto, CA.

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