Planarizeed multi-level interconnect scheme with embedded low-di

Details Planarizeed multi-level interconnect scheme with embedded low-di Planarizeed multi-level interconnect scheme with embedded low-di

1995-05-31

1997-01-07

Tsai, H. Jey

Fishing, trapping, and vermin destroying

437189, H01L 2144, H01L 2148

Patent

active

055916775

ABSTRACT:
A multi-level interconnect structure and method. A first plurality of interconnect lines (14) is located on an insulator layer (12) of semiconductor body (10). A first layer of low dielectric constant material (20), such as an organic polymer, fills an area between the first plurality of interconnect lines (14a-c). The first layer of low dielectric constant material (20) has a height not greater than a height of the first plurality of interconnect lines (14). A first layer of silicon dioxide (18) covers the first layer of low dielectric constant material (20) and the first plurality of interconnect lines (14).

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