Tightly coupled, low overhead RAM built-in self-test logic with

Details Tightly coupled, low overhead RAM built-in self-test logic with Tightly coupled, low overhead RAM built-in self-test logic with

1990-09-19

1993-11-02

Beausoliel, Jr., Robert W.

Excavating

371 211, 371 225, 371 27, 365201, G11C 2900

Patent

active

052589862

ABSTRACT:
RAM Built-In Self-Test logic is presented that utilizes a linear feedback shift register (LFSR) to generate data. Preferably, an LFSR is also utilized for address generation during memory self-testing. More than one cycle is implemented with offset of successive data sequences relative to address sequences to increase fault coverage. Memory storage is utilized in the data generation to enable a reduced area of the data generation circuitry.

REFERENCES:
patent: 3751649 (1973-08-01), Hart, Jr.
patent: 4965799 (1990-10-01), Green et al.
patent: 5033048 (1991-07-01), Pierce et al.
patent: 5053698 (1991-10-01), Ueda
"Signature analysis: A New Digital Field Service Method" Robert A. Frohwerk, Hewlett-Packard Company 1977, pp. 2-14.
"The Polynominal Counter Design Teechnique With Applications in Four-Phase Logic" Donald L. Moon, pp. 135-143, 1968.
"Built-in Test for RAMs" Bardell, Jr. et al., IBM Corp. 1988, pp. 29-36.
"An Optimal Algorithm for Testing Stuck at Faults in RAMs" Knaizuk et al.
"Signature Analysis Concepts, Examples and Guidelines" Hans J. Nadig, pp. 15-21.

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