Shift circuit for double word length data

Details Shift circuit for double word length data Shift circuit for double word length data

1983-04-14

1986-12-23

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 700

Patent

active

046317031

ABSTRACT:
According to a shift circuit of the present invention, two single-word length data shifters of 2.sup.n bits are arranged in parallel. Further, a selective output section is provided to selectively supply the upper 2.sup.n bits or the lower 2.sup.n bits of the double-word length data of 2.sup.n+1 bits, sign of the data and constant to an individual section in accordance with the number of the shift and the type of shift such as the shift direction, arithmetic shift or logical shift. One shifter produces the upper 2.sup.n bits of the shifted data as a result of the shift operation of the double-word length data of 2.sup.n+1 bits, and the other shifter produces the lower 2.sup.n bits thereof while the two shifters operate independently in accordance with the same contents of a shifting number register.

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National Semiconductor, CMOS Databook 1981, p. 1:47.
Sippl, Charles and Roger, Computer Dictionary and Handbook, Howard W. Sams & Co., Indianapolis 1980, p. 452.

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