Method and apparatus for controlling simultaneous switching outp

Details Method and apparatus for controlling simultaneous switching outp Method and apparatus for controlling simultaneous switching outp

1991-05-01

1993-07-20

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, 3072722, 307592, H03K 1716, H03K 1900

Patent

active

052296571

ABSTRACT:
An integrated circuit limits simultaneous switching output noise. Within the integrated circuit, a plurality of output pads are connected to an output holding register. The output holding register includes a plurality of flip-flops. Each flip-flop has a clock input, a data input, and a data output. The data output is connected to an output pad from the plurality of output pads. Various amounts of propagation delay are introduced in a clock signal before the clock signal reaches the clock inputs of the flip-flops.

REFERENCES:
patent: 4570082 (1986-02-01), Maley et al.
patent: 4857765 (1989-08-01), Cahill et al.
patent: 4879718 (1989-11-01), Sanner
patent: 4929850 (1990-05-01), Breuninger
patent: 4970405 (1990-11-01), Hagiwara
patent: 4982118 (1991-01-01), Lloyd
patent: 5055706 (1991-10-01), Nakai et al.

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