Method for making vertical channel field controlled device emplo

Details Method for making vertical channel field controlled device emplo Method for making vertical channel field controlled device emplo

1985-01-17

1986-05-13

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29580, 148175, 357 22, H01L 2120

Patent

active

045877122

ABSTRACT:
A vertical channel junction gate electric field controlled device (e.g., a field effect transistor, or a field controlled thyristor) includes a semiconductor base region layer, and a plurality of grooves having vertical walls formed in the upper surface of the base region layer. Between the grooves, generally on the upper surface of the base region layer, are upper electrode regions, for example, source electrode regions or cathode electrode regions. Recessed in the grooves are junction gate regions. Upper electrode terminal metallization is evaporated generally on the upper device layer, and gate terminal metallization is over the junction gate regions in the grooves. The disclosed structure thus has continuous metallization along the recessed gate regions for a low-resistance gate connection. The structure facilitates fabrication by methods, also disclosed, which avoid any critical photolithographic alignment steps in masking to define the location of the source (or cathode) and gate regions, and avoid the need for any mask or mask alignment for metal definition when forming electrode metallization.

REFERENCES:
patent: 3938241 (1976-02-01), George et al.
patent: 3953879 (1976-04-01), O'Connor-d'Arlach et al.
patent: 4343015 (1982-08-01), Baliga et al.

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