Process for high density VLSI circuits, having self-aligned gate

Details Process for high density VLSI circuits, having self-aligned gate Process for high density VLSI circuits, having self-aligned gate

1984-08-06

1986-05-13

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29577C, 29578, 148DIG156, 156653, 357 239, 357 54, 357 59, H01L 2190

Patent

active

045877114

ABSTRACT:
A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different etch characteristics permits selective oxidation of desired portions only of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliability.

REFERENCES:
patent: 3793090 (1974-02-01), Barile et al.
patent: 3837935 (1974-09-01), Maeda et al.
patent: 4021789 (1977-05-01), Furman et al.
patent: 4277881 (1981-07-01), Godejahn, Jr.
Tanigaki, Y. et al., "A New Self-Aligned Contact Technology" in J. Electrochemical Soc.: Sol. St. Sci. and Tech., vol. 125, No. 3, 3-1978, pp. 471-472.
Chappelow, R. E. et al., "Complex Insulator Layer Processing" in IBM Tech. Discl. Bull., vol. 16, No. 8, 1-1974, p. 2683.

Affiliated with

Also associated with

Rating

Process for high density VLSI circuits, having self-aligned gate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for high density VLSI circuits, having self-aligned gate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for high density VLSI circuits, having self-aligned gate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1762820