Trench isolation process with reduced topography

Details Trench isolation process with reduced topography Trench isolation process with reduced topography

1991-05-22

1993-06-29

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

257622, H01L 2702

Patent

active

052237362

ABSTRACT:
A structure for and method of forming a trench in a semiconductor body is disclosed herein. A field oxide 16 is grown over a portion of n-well 8 where trench 26 is to be formed. Nitride layer 20 and TEOS oxide layer 22 are deposited. Resist 24 is patterned and TEOS layer 22, nitride layer 20, and field oxide layer 16 are etched. Resist 24 is removed and trench 26 is etched through n-well 8 and into substrate 4. Thin oxide 28 is then grown on the sidewalls of trench 26. Polysilicon is deposited into trench 26 and etched back to form polysilicon plug 30. Sidewall oxide 32, to prevent voids in the topography of trench 26, is formed on top of polysilicon plug 30 along the outer edges of trench 26. To prevent leakage into trench 26, a thick thermal oxide cap 34 is grown over trench 26.

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patent: 5017999 (1991-05-01), Roisen et al.
patent: 5061653 (1991-10-01), Teng

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