Method for manufacturing a multi-layered interconnection structu

Details Method for manufacturing a multi-layered interconnection structu Method for manufacturing a multi-layered interconnection structu

1992-02-06

1993-11-02

Maples, John S.

Fishing, trapping, and vermin destroying

437194, H01L 21441

Patent

active

052583295

ABSTRACT:
A semiconductor integrated circuit device and its manufacturing method are disclosed, the method comprising the steps of forming, over a semiconductor substrate, a first interconnection layer which involves a step-like surface, forming, over a first interconnection layer, an insulating layer and planarizing the surface of the second insulating layer, providing a plurality of via holes of different depths in the insulating layer reaching the first interconnection layer, subsequent to the step, implanting an impurity ion in the first interconnection layer such that an electronegativity in the first interconnection layer varies in accordance with the depths of the via holes, depositing a metal film in the via holes, and forming a second interconnection layer over the insulating layer so as to be connected to the first interconnection layer by the deposited metal film in the via holes.

REFERENCES:
patent: 4265935 (1981-05-01), Hall
patent: 5063175 (1991-11-01), Broadbent

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