Topside analysis of a multi-layer integrated circuit die mounted

Details Topside analysis of a multi-layer integrated circuit die mounted Topside analysis of a multi-layer integrated circuit die mounted

1998-07-27

1999-05-18

Bowers, Charles

Semiconductor device manufacturing: process

With measuring or testing

Packaging or treatment of packaged semiconductor

438109, 438125, 257692, 257693, 257694, H01J37/30

Patent

active

059044896

ABSTRACT:
Aspects for topside analysis of an integrated circuit die mounted in a flip-chip orientation are described. In an exemplary method aspect, the method includes isolating the multi-layer integrated circuit die from the flip-chip package, and exposing the multilayer integrated circuit die. The method further includes testing selected areas of the multi-layer integrated circuit die from a topside utilizing critical paths placed in a predetermined arrangement around edges of the multi-layer integrated circuit die.

REFERENCES:
patent: 5155067 (1992-10-01), Wood et al.
patent: 5336649 (1994-08-01), Kinsman et al.
patent: 5766978 (1998-06-01), Johnson
patent: 5786701 (1998-07-01), Pedder
patent: 5789930 (1998-08-01), Isaacs et al.
patent: 5801432 (1998-09-01), Rostoker et al.
patent: 5807763 (1998-09-01), Motika et al.
patent: 5821549 (1998-10-01), Talbot et al.

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