High frequency clock pulse counter

Details High frequency clock pulse counter High frequency clock pulse counter

1989-11-22

1991-02-05

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Counter controlled counter

377 37, 377 55, 377 56, 377 28, H03K 2102, H03K 2110, H03K 2140

Patent

active

049911864

ABSTRACT:
A counter comprising n one-bit cells receiving a clock signal (CK0) having a frequency f to be counted and a read transfer order (TO). The lower rank p cells operate at the frequency f and the n-p higher rank cells at a frequency f/2.sup.p. The lower rank p cells (51-53) directly receive the clock signal (CK0) at frequency f and, if necessary, the transfer order (TO) synchronized in correspondence with CK0. The higher rank n-p cells receive as a clock signal at frequency f/2.sup.p, a signal (CK1) delayed by at least two periods of said clock signal CK0 and at the most by (2p-2) pulses CK0 with respect to the counting signal of the highest rank cell among the lower rank p cells.

REFERENCES:
patent: 3982108 (1975-03-01), Horsley
patent: 4160154 (1979-07-01), Jennings
patent: 4499589 (1985-02-01), Geesen
patent: 4519091 (1985-05-01), Chu et al.
NASA Tech Briefs, "Simple Logic Reads Out During Counting", Electronic Design 11, May 24, 1967, p. 107.

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