Static information storage and retrieval – Addressing
Patent
1987-02-13
1988-09-20
Fears, Terrell W.
Static information storage and retrieval
Addressing
364200, G11C 800, G06F 700
Patent
active
047730480
ABSTRACT:
A semiconductor memory device comprises an address signal generator for generating address signals including row and column address signals, and an additional address signal to indicate if the column address is even- or odd-numbered; even- and odd-numbered bank memories with a plurality of word areas each including n bit areas; row decoder which in response to a row address signal, specifies the row address position in the even- or odd-numbered bank memory; and a column decoder which in response to the address signal, specifies the column address positions in the even- and odd-numbered bank memories. The column decoder responds to the address signal representing the column address 2j or (2j+1), to specify the column address position [2j] or [2j+2] in the even-numbered memory, and at the same time specifies the column address position [2j+1] in the odd-numbered bank memory.
REFERENCES:
patent: 3402398 (1968-09-01), Koerner et al.
patent: 3644906 (1972-02-01), Weinberger
patent: 4163281 (1979-07-01), Steinga
patent: 4429375 (1984-01-01), Kobayashi et al.
patent: 4660181 (1987-04-01), Saito et al.
patent: 4667308 (1987-05-01), Hayes et al.
Fears Terrell W.
Kabushiki Kaisha Toshiba
Koval Melissa J.
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