Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Patent
1987-05-05
1989-10-17
Moffitt, James W.
Static information storage and retrieval
Addressing
Including particular address buffer or latch circuit...
36518907, 307358, G11C 800
Patent
active
048751952
ABSTRACT:
A highly-integrated semiconductor dynamic random-acess memory is disclosed wherein a reference voltage-generating circuit is connected by voltage-transmission lines to a row-address buffer and a column-address buffer. The reference voltage-generating circuit receives a power-supply voltage and generates first and second reference voltages which are different, by different values, from an ordinary reference potential level. These reference voltages are supplied to the address buffers through the voltage-transmission lines. The first and second reference voltages are adjusted to compensate for a potential deviation which occurs on the voltage-transmission lines. Therefore, even when either reference voltage fluctuates due to an increase in the coupling capacitance between the substrate of the dynamic random-access memory, on the one hand, and the voltage-transmission lines, on the other, both address buffers are prevented from malfunctioning.
REFERENCES:
patent: 4477736 (1984-10-01), Onishi
Momodomi Masaki
Sakui Koji
Kabushiki Kaisha Toshiba
Moffitt James W.
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