Microcomputer with disconnected, open, independent, bimemory arc

Details Microcomputer with disconnected, open, independent, bimemory arc Microcomputer with disconnected, open, independent, bimemory arc

1987-06-12

1989-10-17

Clark, David L.

Boots, shoes, and leggings

G06F 1300

Patent

active

048751545

ABSTRACT:
A Bimemory Independent CPU (BICPU) microcomputer which is comprised of a known CPU chip provided with additional circuitry to enable CPU to interact in a multi BICPU microcomputer system. Each BICPU microcomputer in a system is supplied with an assigned standard memory mechanically and logically connected to it's BICPU's "A" bus circuits. The BICPU microcomputer is also provided with connectors enabling the CPU to be connected to system buses. Any number of BICPU microcomputers can be logically chained, linked and treed in a simple logical bimemory independent pattern infinitely in as many dimensions as is reasonably desired, using one standard set of dedicated, simple, single line conductors (system buses) to mechanically interconnect any "B" or "C" bus curcuits of two different BICPU microcomputers.

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MOS Technology Manuals-Programming and Hardware, MOS Technology, Inc., Jan. 1976.
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"A Multicomputer System with Dynamic Architecture"-IEEE Trans. Computers, vol. C-28, No. 10, 10-1979, pp. 704-720, S. I. Karteshev and S. P. Karteshev.
Budzinski R., Linn J., and Thatti S., "A Restructurable Integrated Circuit for Implementing Programmable Digital Systems ", Computer, Mar. 1982, pp. 43-54.

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